The function generators in class have a Thevenin Equivalent output resistance $\backslash (\backslash$mathrm$\{$R$\}\_\{\backslash$mathrm$\{$TH$\}\}=50\backslash$Omega $\backslash )$ we are going to configure the output voltage to be a square wave with a magnitude of $\backslash (\backslash$mathrm$\{$V$\}\_\{\backslash$mathrm$\{$IH$\}\}=3\mathrm{.}3\backslash$mathrm$\{$~V$\}\backslash ).$ If put under a capacitive load, the schematic can be modeled with Circuit $1.$

Circuit $1$: Digital IO under load

Part $1$: Maximum Capacitive loads for digital signals

$1.$ Derive Equation $4$ by using Equations $2$ and $3.$

$2.$ In order to prevent digital distortion on the output voltage Vout. It must hold that trive is less than $\backslash (10\backslash \%\backslash )$ of ton. More formally this states that trise $\backslash (<mn>0</mn><mn>.</mn><mn>1</mn><mtext></mtext><mi>\backslash </mi><mi>)</mi>$ ton.

a$.$ Use the equation: trise $\backslash (<mn>0</mn><mn>.</mn><mn>1</mn><mtext></mtext><mi>\backslash </mi>$mathrm$\{$ton$\}\backslash ),$ to calculate the maximum capacitive load $\backslash (\backslash$mathrm$\{$Cl$\}\_\{\backslash$mathrm$\{$I$\}\}\backslash )$ for Circuit $1.$

b$.$ Round your calculated $\backslash (\backslash$mathrm$\{$Cl$\}\_\{2\}\backslash )$ to the closest standard capacitor values. Call the new capacitance ClMax.

i$.$ A link to standard capacitor values can be found here.