The Intel Pentium 4 had a 4K entry branch target buffer (BTB) for branch prediction, tracking the direction of up to 4096 branches, plus a 512 entry trace cache BTB (the trace cache is an L1 instruction cache holding instructions already decoded into their corresponding microcode). They claim these reduced the overall misprediction rate by 1/3 as compared to the Pentium III's. The Pentium 4's misprediction penalty was 19 cycles at 2.4 GHz, while the Pentium III penalty was 9 cycles at 1.4GHz.

On a given workload, 20% of the instructions are branches, which the Pentium III predicts correctly 90% of the time.

2A) Pentium III Branch Cost

What is slowdown as compared to the ideal pipeline for the Pentium III?

2B) Pentium 4 prediction rate

Given this data, what was the branch prediction rate for the Pentium 4?

2C) Pentium 4 Branch Cost

What is the slowdown as compared the ideal pipeline for the Pentium 4?

2D) Ideal Speedup

Considering only the improvement in clock speed (and not the effects of branch prediction or any other improvements), what is the ideal speedup expected for the Pentium 4 over the Pentium III? Note that the difference in pipeline depths is already reflected in the change in clock speeds, so should not appear in your answer.

2E) Speedup with Branch Prediction

What is the overall speedup considering both the change in clock rate and the effect of branch prediction and branch penalties (but not considering other architectural improvements) of the Pentium 4 as compared to the Pentium III?