Question: The logic latencies for individual stages in a processor are listed in the following table. IF ID EXE MEM WB 350ps 400ps 370ps 450ps 200ps

The logic latencies for individual stages in a processor are listed in the following table.

IF	ID	EXE	MEM	WB
350ps	400ps	370ps	450ps	200ps

What is total latency of an ARM LDR instruction in a pipelined processor? What is the throughput of a large series of LDR instructions with no pipeling hazards? Express your answer in millions of instructions per second (MIPs).

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