The MIPS has only three-operand format for its register-register operations. Many operations might use the same destination register as one of the sources. For example 6) ADD R1, R1, R2 We could introduce a new instruction format into the MIPS called R_2 that has only two operands and has 24 bits in length. The above instruction would be change to: ADD R1, R2 Assume the following instruction frequency: Instruction Register-Register ALU operations Immediate ALU operations Loads Stores Branches Frequency 19.7% 27.2% 22.8% 14.3% 16.0% If 55% of the register-register ALU operations can take advantage of the R-2 format, how much would the instruction bandwidth for the MIPS be reduced