The next sequential circuit we will build is a basic form of memory. We will create an SR Flip Flop/Latch. Even though logic.ly exposes a single component block diagram for a SR Flip-Flop, we will build it using only NOR gates. The layout of the circuit for this is given below. When you build this, you will have two inputs, one of which will be your Set, the other will be your Reset. When you build it, determine which input you will refer to as S and which to R. It doesn't matter which is which, as long as you are consistent. Create and fill in the values for a state table which includes values for S, R, the Previous Q, the Current Q, and Current Q'. Do Figure 3: SR Flip Flop Include a labeled snip of your completed S/R Flip Flop in your lab submission. SR Flip Flop with DeMorgan's Law Using DeMorgan's Law, use AND gates (and any other required components) to build the SR Flip Flop. Include a labeled snip of your completed circuit in your lab submission. The next sequential circuit we will build is a basic form of memory. We will create an SR Flip Flop/Latch. Even though logic.ly exposes a single component block diagram for a SR Flip-Flop, we will build it using only NOR gates. The layout of the circuit for this is given below. When you build this, you will have two inputs, one of which will be your Set, the other will be your Reset. When you build it, determine which input you will refer to as S and which to R. It doesn't matter which is which, as long as you are consistent. Create and fill in the values for a state table which includes values for S, R, the Previous Q, the Current Q, and Current Q'. Do Figure 3: SR Flip Flop Include a labeled snip of your completed S/R Flip Flop in your lab submission. SR Flip Flop with DeMorgan's Law Using DeMorgan's Law, use AND gates (and any other required components) to build the SR Flip Flop. Include a labeled snip of your completed circuit in your lab submission.