The parasitic capacitance of BL in DRAM memory array is 55 fF while a cell capacitor stores only 7 fF. VDD=1.0V

A. What is the maximum VBL(|VBL-VBLB|)? B. If the storage node potential for data 1 varies with time as VSN = VDD*[1-0.7exp(-t/t0)], and 50% of cell charges leak in 0.2 sec, how long does it takes the storage node potential drops as low as half VDD? C. What is the tREF,max when the offset of BLSA is 25mV?

The parasitic capacitance of BL in DRAM memory array is 55 fF while a cell capacitor stores only 7 fF. VDD-1.0V A. What is the maximum AVBLI VBL-VBLBI)? B. If the storage node potential for data T varies with time as VSN-VDD* [1-0.7exp(- t/to), and 50% of cell charges leak in 0.2 sec, how long does it takes the storage node potential drops as low as half VDD? C. What is the tREF.max when the offset of BLSA is 25mV? The parasitic capacitance of BL in DRAM memory array is 55 fF while a cell capacitor stores only 7 fF. VDD-1.0V A. What is the maximum AVBLI VBL-VBLBI)? B. If the storage node potential for data T varies with time as VSN-VDD* [1-0.7exp(- t/to), and 50% of cell charges leak in 0.2 sec, how long does it takes the storage node potential drops as low as half VDD? C. What is the tREF.max when the offset of BLSA is 25mV