The processor must use the following interface, name and ports.

Module name $-$ cpu

Ports

Name Direction Width Details

rst$\_$n Input $0$:$0$ Active low reset

clk Input $0$:$0$ Clock

imem$\_$addr Output $31$:$0$ Instruction memory address

imem$\_$insn Input $31$:$0$ Instruction from Instruction memory

dmem$\_$addr Output $31$:$0$ Data memory address

dmem$\_$data InOut $31$:$0$ Data to$/$ from data memory

dmem$\_$wen Output $0$:$0$ Write enable for data memory $(1$ for Store, $0$ for

Load$)$