The program described below runs on a multiple issue processor with a $3$ level CPU cache, a $4$ GHz $(1$GHz$=10^9$Hz$)$ clock frequency, and the following performance metrics: $($IPC: instructions per cycle$)$ Level Miss Penalty R$/$W Data Miss Rate L$1$ cache $25\%$ Instruction Miss Rate L$2$ cache $2\%2\%$ Main $1\mathrm{.}3\%51000\mathrm{.}3\%$ Instruction Class $0\mathrm{.}1\%$ Instruction Count Branch$/$Jump $2105$ IPC Load$/$Store $1\mathrm{.}14\mathrm{.}1104$ Arithmetic $0\mathrm{.}93\mathrm{.}6106$ Float Add $1\mathrm{.}55\mathrm{.}51050\mathrm{.}25$ a$).(15$ pts$)$ What is the base CPU time of the program $($without consider the memory stall time$)?$ b$).(15$ pts$)$ What is the amount of time $($in second$)$ consumed by memory$-$stall clock cycles? Assume equal read$/$write miss penalty and negligible write buffer stalls. $($Hint: Memory stall cycles $=$ Memory accesses $*$ miss rate $*$ miss penalty$)$ c$).(15$ pts$)$ What is the total CPU time of the program $($in second$)?($Hint: CPU time $=($CPU execution cycles $+$ Memory stall cycles$)/$ clock rate$)$ d$).(15$ pts$)$ What percentage of CPU time was taken by memory stall cycles?