The program described below runs on a multiple issue processor with a $3-$level CPU cache, a $4$ GHz$(1$GHz$=109$Hz$)$ clock frequency, and the following performance metrics: $($IPC: instructions per cycle$)$Level Miss Penalty R$/$W Data Miss Rate Instruction Miss RateL$1$ cache $25\%2\%$L$2$ cache $52\%1\mathrm{.}3\%$Main $1000\mathrm{.}3\%0\mathrm{.}1\%$Instruction Class Instruction Count IPCBranch$/$Jump $2\backslash$times $1051\mathrm{.}1$Load$/$Store $4\mathrm{.}1\backslash$times $1040\mathrm{.}9$Arithmetic $3\mathrm{.}6\backslash$times $1061\mathrm{.}5$Float Add $5\mathrm{.}5\backslash$times $1050\mathrm{.}25$a$).(5$ pts$)$ What is the base CPU time of the program $($without consider the memory stall time$)?$b$).(5$ pts$)$ What is the amount of time $($in second$)$ consumed by memory$-$stall clock cycles?Assume equal read$/$write miss penalty and negligible write buffer stalls. $($Hint: Memory stallcycles $=$ Memory accesses $*$ miss rate $*$ miss penalty$)$