The verilog file, counters.v, contains the four counters, a count by 3, a count by 5, a count by 3 that clamps at the largest value, a count by 5 that clamps at tehe largest value. The test bench is tb_counters.v.

The next state logic of each counter is described using behavioural code, replace this code with combination/arithmetic description.

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`timescale 1ns / 1ns module dff( q, d, clk); parameter N = 8; output reg [N-1:0] q; input [N-1:0] d; input clk; always @(posedge clk) begin q = d; end endmodule module countby3( count, reset, clock ); output [5:0] count; input reset, clock; wire [5:0] count_d; dff #(6) state( count, count_d, clock); // replace with arithmetic and/or combinational logic assign count_d = reset ? 0 : count + 3; endmodule module countby3clamp( count, clamp, reset, clock ); output [5:0] count; output clamp; input reset, clock; wire [5:0] count_d; dff #(6) state( count, count_d, clock); // replace with arithmetic and/or combinational logic assign clamp = count == 63; assign count_d = reset ? 0 : count + (clamp ? 0 : 3); endmodule module countby5( count, reset, clock ); output [5:0] count; input reset, clock; wire [5:0] count_d; dff #(6) state( count, count_d, clock); // replace with arithmetic and/or combinational logic assign count_d = reset ? 0 : count + 5; endmodule module countby5clamp( count, clamp, reset, clock ); output [5:0] count; output clamp; input reset, clock; wire [5:0] count_d; dff #(6) state( count, count_d, clock); // replace with arithmetic and/or combinational logic assign clamp = count == 60; assign count_d = reset ? 0 : count + (clamp ? 0 : 5); endmodule 

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`timescale 1ns / 1ns module main; wire [5:0] count5, count3, count3clamp, count5clamp; wire clamp3, clamp5; reg reset5=1, reset3=1, reset3c=1, reset5c=1; reg clock=0; always #2 clock = ~clock; countby5 five_c( count5, reset5, clock); countby3 three_c( count3, reset3, clock); countby3clamp threec_c( count3clamp, clamp3, reset3c, clock); countby5clamp fivec_c( count5clamp, clamp5, reset5c, clock); initial begin $display("counter results"); $monitor("t=%04d c5=%d c5c=%d c3=%d c3c=%d", $time, count5, count5clamp, count3, count3clamp ); #6; // release reset reset5 = 0; reset3 = 0; reset3c = 0; reset5c = 0; #96 $finish; end endmodule 

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The next state logic of each counter is described using behavioural code, replace this code with combination/arithmetic description.