There are syntax problems in the following Verilog code. That is, it will not even compile...

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There are syntax problems in the following Verilog code. That is, it will not even compile without errors. Correct those compile problems and rewrite the code. Mark where the errors are. ALSO fix the indentation. That is, write your code with correct indentation. module ( input flag1 flag3, input [1:0] flag2, input reset, output [1:0] flop2Nxt) ) assign flop2Nxt = flop always @posedge clock flop <= #1 flopNxt flop2 <= #1 flop2Nxt assign flag4 = flag1 && flag3 always @* begin flop; flopNxt if(reset) flopNxt = 1; if(flag1== 1) flopNxt = 2; else if end if(~flag4) (flag2= 2'b10) flopNxt = 3 flopNxt = 0; There are syntax problems in the following Verilog code. That is, it will not even compile without errors. Correct those compile problems and rewrite the code. Mark where the errors are. ALSO fix the indentation. That is, write your code with correct indentation. module ( input flag1 flag3, input [1:0] flag2, input reset, output [1:0] flop2Nxt) ) assign flop2Nxt = flop always @posedge clock flop <= #1 flopNxt flop2 <= #1 flop2Nxt assign flag4 = flag1 && flag3 always @* begin flop; flopNxt if(reset) flopNxt = 1; if(flag1== 1) flopNxt = 2; else if end if(~flag4) (flag2= 2'b10) flopNxt = 3 flopNxt = 0;

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