Complete the following Verilog code to implement a test bench for the sequential circuit SMQ1. Assume that the Verilog code for the SMQ1 sequential circuit module is already available. Use a clock with a 50-ns half period. Your test bench should test the circuit for the input sequence X = 1, 0, 0, 1, 1. Assume that the correct output sequence for this input sequence is 1, 1, 0, 1, 0. Use a single concurrent statement to generate the X sequence. The test bench should read the values of output Z at the proper times and should compare them with the correct values of Z. The correct answer is initialized as a constant:

answer = 11010;

The port signal correct should be set to TRUE if the answer is correct; otherwise, it should be set to FALSE. Make sure that you read Z at the correct time. Use wait statements in your test bench.
module testSMQ1(correct);
output reg correct;
reg CLK;
reg [4:0] X;
reg [4:0] Z;
reg [4:0] answer;
initial
begin
correct = 1;
X = 5'b10011;
Z = 5'b11010;
answer = 5'b11010;
end
.
.
.
.
endmodule