these are the $3$codes that i wrote implement Digital Stopwatch

Design a stopwatch that can measure time in seconds and milliseconds. Include start, stop, and reset functionalities. ### plz let me know it there's any modification to let them work properly on the seven segment desplay on the fpga de$10-$lite board.Projects must include a graphical representation of the design, such as a State Machine $($SM$)$chart or a State Graph.

$1$ library ieee;

use ieee.std$\_$logic$\_1164.$a$11$;

use ieee.numeric$\_$std$.$a$11$;

$$entity stopwatch$\_$top is

port $($

clk : in std$\_$logic;

reset : in std$\_$logic;

start$\_$stop : in std$\_$logic;

clear : in std$\_$logic;

seg$7\_$display : out std$\_$logic$\_$vector$(6$ downto $0)$;

anode$\_$enable : out std$\_$logic$\_$vector$(4$ downto $0)\text{'}--5-$bit vector for $5$ displays

$)$;

end stopwatch$\_$top;

garchitecture rtl of stopwatch$\_$top is

signal enable : std$\_$logic;

signal state$\_$led : std$\_$logic$\_$vector$(1$ downto $0)$;

signal ms$\_$counter : unsigned$(9$ downto $0)$ :$=($others $=>\text{'}0\text{'})$; $--10-$bit counter for milliseconds $(0-999)$

signal sec$\_$counter : unsigned$(5$ downto $0)$ :$=($others $=>\text{'}0\text{'})$;

signal min$\_$counter : unsigned$(5$ downto $0)$ :$=($others $=>\text{'}0\text{'})$;

signal sec$\_$ones, sec$\_$tens, min$\_$ones, min$\_$tens, ms$\_$ones, ms$\_$tens : unsigned$(3$ downto $0)$;

signal current$\_$display : unsigned$(3$ downto $0)$;

signal mux$\_$select : unsigned$(2$ downto $0)$ :$=($others $=>\text{'}0\text{'})$; $--$ Update for $5$ displays

signal clk$\_$div : unsigned$(19$ downto $0)$ :$=($others $=>\text{'}0\text{'})$;

signal mux$\_$clk : std$\_$logic;

@begin

$--$ Instantiate the FSM

fsm$\_$inst : entity work.stopwatch$\_$fsm

port map $($

clk $=>$ clk$,$

reset $=>$ reset,

start$\_$stop $=>$ start$\_$stop,

clear $=>$ clear,

enable $=>$ enab$1$e$,$

state$\_$led $=>$ state$\_$led

$)$;

$--$ Milliseconds counter process

process $($clk$.$ reset$)$

$```$

$86-$ end process;

mux$\_$clk clk$\_$div$(19)$; $--$ Adjust based on your clock frequency

$--$ Multiplexing control

process $($mux$\_$clk$,$ reset$)$

begin

if reset $=\text{'}1\text{'}$ then

mux$\_$select others $=>\text{'}0\text{'})$;

elsif rising$\_$edge$($mux$\_$clk$)$ then

mux$\_$select mux$\_$select $+1$;

end if;

end process;

$--$ Current display value selection

process $($mux$\_$select, sec$\_$ones, sec$\_$tens, min$\_$ones, min$\_$tens, ms$\_$ones, ms$\_$tens$)$

begin

case mux$\_$select is

when $"000"=>$ current$\_$display ms$\_$ones; $--$ Milliseconds, ones place

when $"001"=>$ current$\_$display ms$\_$tens; $--$ Milliseconds, tens place

when $"010"=>$ current$\_$display sec$\_$ones; $--$ Seconds, ones place

when $"011"=>$ current$\_$display sec$\_$tens; $--$ Seconds, tens place

when $"100"=>$ current$\_$display min$\_$ones; $--$ Minutes, ones place

when $"101"=>$ current$\_$display min$\_$tens; $--$ Minutes, tens place

when others $=>$ current$\_$display others $=>\text{'}0\text{'})$;

end case;

end process;

$--$ Instantiate the $7-$segment display module

seg$7\_$inst : entity work.seg$7$

port map $($

a $=>$ std$\_$logic$\_$vector$($current$\_$display$),$

en $=>\text{'}1\text{'},$

$)$;

q $=>$ seg$7\_$display

$--$ Anode enable for multiplexing $5$ displays

anode$\_$enable when mux$\_$select $="000"$ else $--$ For display $1($ms ones$)$

$"11101"$ when mux$\_$select $="001"$ else $--$ For display $2($ms tens$)$

$"11011"$ when mux$\_$select $="010"$ else $--$ For display $3($sec ones$)$

$"10111",$ when mux$\_$select $="011"$ else $--$ For display $4($sec tens$)$

$"01111"$; $--$ For display $5($min ones, assuming $5$th display$)$

end rtl;

$``````$

library ieee;

use ieee.std$\_$logic$\_1164.$al$1$;

use ieee.numeric$\_$std$.$ali;

$--$ Entity

gentity seg$7$ is

port $($

a : in std$\_$logic$\_$vector $(3$ downto $0)$;

en : in st$\backslash$overline$\{$d$\_$logic;$\}$

$($end $)$;

$--$ Architecture

@architecture rtl of seg$7$ is

type rom is array $(0$ to $9)$ of std$\_$logic$\_$vector $(6$ downto $0)$;

constant seg$\_$table : rom :$=($

$"0000001",--0$

$"1001111",--1$

$"0010010",--2$

$"0000110",--3$

$"1001100",--4$

$"0100100",--5$

$"0100000",--6$

$"0001111",--7$

$"0000000",\text{'}--8$

$"0000100"--9$

$)$;

@begin

process $($a$,$ en$)$

begin

if en $=\text{'}1\text{'}$ then

if a $="1010"$ then

else

q ;

q seg$\_$table$($to$\_$integer$($unsigned$($a$)))$;

end if;

else

q;

end if;

end process;

end rtl;

$```$

$```$

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$```$

$```$

library ieee;

use ieee.std$\_$logic$\_1164.$a$11$;

use ieee.numeric$\_$std$.$a$11$;

$$entity stopwatch$\_$fsm is

port $($

clk : in std$\_$logic;

reset : in std$\_$logic;

start$\_$stop : in std$\_$logic; $--$ Input to toggle start$/$stop

clear : in std$\_$logic; $--$ Input to reset the stopwatch

enable: out std$\_$logic; $--$ Output to enable the counters

state$\_$led : out std$\_$logic$\_$vector$(1$ downto $0)--$ State indicator $($optiona$1)$

$-$end stopwatch$\_$fsm;

@architecture behavioral of stopwatch$\_$fsm is

$--$ Define the states

type state$\_$type is $($IDLE$,$ RUNNING, PAUSED$)$;

signa$1$ current$\_$state, next$\_$state : state$\_$type;

$--$ Internal signals

signal start$\_$stop$\_$edge : std$\_$logic :$=\text{'}0\text{'}$;

signal last$\_$start$\_$stop : std$\_$logic :$=\text{'}0\text{'}$;

$$begin

$--$ State LED output $($optional$,$ for debugging$)$

state$\_$led std$\_$logic$\_$vector'$($to$\_$unsigned$($state$\_$type'pos$($current$\_$state$),2))$;

$--$ Edge detection for the start$/$stop button

process $($clk$)$

begin

if rising$\_$edge$($clk$)$ then

start$\_$stop$\_$edge start$\_$stop and not last$\_$start$\_$stop;

last$\_$start$\_$stop start$\_$stop;

end if;

end process;

$--$ State t