These ares still wrong in some aspect please help

$12$ pts$)$ Consider a datapath similar to the one in Figure $4\mathrm{.}21$ or slide $24.$ Assume that logic

blocks needed to implement a processor$$s datapath have the following latencies:

I$-$Mem Add Mux ALU Regs D$-$Mem Sign$-$Extend Shift$-$Left$-2$

I$-$Mem Add Mux ALU Regs D$-$Mem Imm$-$Gen Shift$-$Left$-1$

$250$ps $150$ps $25$ps $200$ps $150$ps $250$ps $50$ps $30$ps

a$.(2$ pts$)$ What is the latency of a R$-$type instruction $($i$.$e$.,$ how long must the clock period be

to ensure that this instruction works correctly$)?$

$250$ps $($I$-$Mem$)+150$ps $($Add$)+25$ps $($Mux$)+200$ps $($ALU$)+150$ps $($Regs$)+250$ps $($D$-$

Mem$)=1025$ps

b$.(2$ pts$)$ What is the latency of ld$?$

$250$ps $($I$-$Mem$)+150$ps $($Add$)+25$ps $($Mux$)+200$ps $($ALU$)+250$ps $($D$-$Mem$)+150$ps

$($Regs$)=1025$ps

c$.(2$ pts$)$ What is the latency of beq?

$250$ps $($I$-$mem$)+150$ps $($Add$)+200$ps $($ALU$)+25$ps $($Mux$)+50$ps $($Imm$-$Gen$)+30$ps

$($Shift$-$L$-$I$)+150$ps $($Add$)=855$ps

d$.(2$ pts$)$ What is its latency of the following I$-$type instruction?

addi x$10,$ x$11,128$

What is its latency?

$250$ps $($I$-$Mem$)+150$ps $($Add$)+25$ps $($Mux$)+200$ps $($ALU$)+150$ps $($Regs$)+50$ps

$($Imm$-$Gen$)+30$ps $($Shift$-$L$-1)=855$ps

e$.(4$ pts$)$ Describe the execution flow of a sd instruction. What is its latency?

$250$ps $($I$-$Mem$)+150$ps $($Add$)+25$ps $($Mux$)+200$ps $($ALU$)+150$ps $($Regs$)+50$ps

$($Imm$-$Gen$)+30$ps $($Shift$-$L$-1)+150$ps $($Add$)+25$ps $($Mux$)+200$ps $($ALU$)+150($Regs$)$

$+250$ps $($Imm$-$Gen$)=1630$ps