This assignment is designed to be filled in directly on the handout. Please use scratch paper while figuring out the solutions. Show your work for problems $2-4.$ For problem $1,$ only provide the requested information. Electronic versions $($PDF and Word$)$ are available on Canvas.

$1.(36$ points, $12$ points each$)$ Here is a series of $16-$bit address references of a word addressable machine:

$\backslash$begin$\{$tabular$\}\{|$l$|$l$|$l$|$l$|\}$

$\backslash$hline Addresses & Hit $/$ miss $($part a$)$ & Hit $/$ miss $($part b$)$ & Hit $/$ miss $($part c$)\backslash \backslash$

$\backslash$hline $0$x$768$a & & & $\backslash \backslash$

$\backslash$hline $0$x$7687$ & & & $\backslash \backslash$

$\backslash$hline $0$x$768$b & & & $\backslash \backslash$

$\backslash$hline $0$x$1$d$36$ & & & $\backslash \backslash$

$\backslash$hline $0$xc$05$e & & & $\backslash \backslash$

$\backslash$hline $0$x$7686$ & & & $\backslash \backslash$

$\backslash$hline $0$x$7688$ & & & $\backslash \backslash$

$\backslash$hline $0$x$768$a & & & $\backslash \backslash$

$\backslash$hline $0$xc$05$e & & & $\backslash \backslash$

$\backslash$hline $0$x$5$f$42$ & & & $\backslash \backslash$

$\backslash$hline $0$x$768$b & & & $\backslash \backslash$

$\backslash$hline $0$x$5$f$43$ & & & $\backslash \backslash$

$\backslash$hline

$\backslash$end$\{$tabular$\}$

For the following cache configurations, indicate if each reference is a hit or miss in the table above. In each case, the cache starts out empty.

a$.$ Direct$-$mapped cache, $16$ word cache $($data portion$),2$ word block size

b$.2-$way set associative cache, $16$ word cache $($data portion$),2$ word block size, LRU eviction algorithm

c$.$ Fully associative, $16$ word cache $($data portion$),4$ word block size, LRU eviction algorithm

Also, list the final contents of the cache. It is only necessary to specify the tag field $($use the term "empty" if the line is still empty$/$invalid$).$ The tag must be written in hexadecimal notation $-$ be sure it has the proper number of bits. As an example, the state of the cache after the first reference for configuration $($a$)$ is given. It is up to you to create the charts for configurations $($b$)$ and $($c$).$

$\backslash$begin$\{$tabular$\}\{|$l$|$l$|\}$

$\backslash$hline Set & Tag $\backslash \backslash$

$\backslash$hline $0$ & empty $\backslash \backslash$

$\backslash$hline $1$ & empty $\backslash \backslash$

$\backslash$hline $2$ & empty $\backslash \backslash$

$\backslash$hline $3$ & empty $\backslash \backslash$

$\backslash$hline $4$ & empty $\backslash \backslash$

$\backslash$hline $5$ & $\backslash (0$ x $768\backslash )\backslash \backslash$

$\backslash$hline $6$ & empty $\backslash \backslash$

$\backslash$hline $7$ & empty $\backslash \backslash$

$\backslash$hline

$\backslash$end$\{$tabular$\}$

Final cache configurations for problem $1$:

a$.$

b$.$

c$.$