This exercise compares the performance of1-issue and 2-issue processors, taking into account the program transformations that can be made to optimize for 2-issue execution. Assume we have the following C program. for (i-0: i- i+-2) When translating into MIPS code, assume that variables are kept in registers as shown in following table, and that all registers except those indicated as Free are used to keep various variables so they cannot be used for anything else. Free r10, rl1, r12 A. Translate this C code into MIPS instructions. Your translation should be direct, i.c. without rearranging instructions to achieve better performance. If the loop exits after exccuting only two iterations, draw a pipeline diagram for your MIPS code from (A) executed on a 2-issue processor whose data path is shown below (Figure 4.69 in the textbook). Assume the processor has perfect branch prediction and can fetch any two instructions (not just consecutive instructions) in the same cycle. B. C. Rearrange your code from (A) to achieve a better performance on a 2-issue statically scheduled processor whose data path is shown below D. Repeat (B), but use your MIPS code from (C) E. What is the speedup of going from an 1-issue processor to a 2-issue processor? Use your code from (A) for both 1-issue and 2-issue processors, and assume that 1,000,000 iterations of the loop are executed. As in (B), assume that the processor has perfect branch prediction, and that a 2-issue processor can fetch any two instructions in the same F. Repeat (E), but assume that, in the 2-issue processor, one of the instructions to be executed in a cycle can be of any kind, and the other must be a non-memory instruction. This exercise compares the performance of1-issue and 2-issue processors, taking into account the program transformations that can be made to optimize for 2-issue execution. Assume we have the following C program. for (i-0: i- i+-2) When translating into MIPS code, assume that variables are kept in registers as shown in following table, and that all registers except those indicated as Free are used to keep various variables so they cannot be used for anything else. Free r10, rl1, r12 A. Translate this C code into MIPS instructions. Your translation should be direct, i.c. without rearranging instructions to achieve better performance. If the loop exits after exccuting only two iterations, draw a pipeline diagram for your MIPS code from (A) executed on a 2-issue processor whose data path is shown below (Figure 4.69 in the textbook). Assume the processor has perfect branch prediction and can fetch any two instructions (not just consecutive instructions) in the same cycle. B. C. Rearrange your code from (A) to achieve a better performance on a 2-issue statically scheduled processor whose data path is shown below D. Repeat (B), but use your MIPS code from (C) E. What is the speedup of going from an 1-issue processor to a 2-issue processor? Use your code from (A) for both 1-issue and 2-issue processors, and assume that 1,000,000 iterations of the loop are executed. As in (B), assume that the processor has perfect branch prediction, and that a 2-issue processor can fetch any two instructions in the same F. Repeat (E), but assume that, in the 2-issue processor, one of the instructions to be executed in a cycle can be of any kind, and the other must be a non-memory instruction