This is a pipelining processor from my computer architecture class.

Question 3 Pipelining a. (5 marks) Assume you have N items to process. If you can pipeline the processing into P steps (perfectly balancing the pipeline), what speedup is achieved? Explain all the steps used to arrive at your answer. b. (5 marks) Consider the following RISCV code add x5,x2,xl lw x3,4(x5) lw x2,0(x2) or x3,x5,x3 sw x3,0(x5) Rewrite this instruction sequence, inserting nop instructions, so it is free from hazards You should assume standard 5-stage pipeline (instruction fetch, instruction decode / register fetch, execute, memory, write-back) with no forwarding or hazard detection If registers are read in the same cycle in which they are written, the new value is returned. Draw a pipeline diagram to illustrate the correctness of your answer. c. (5 marks) Using a figure, explain how the hazard between the "or" and "sw" instructions could be resolved by forwardin d. (5 marks) Explain in detail, the problem solved by the "speculate and kill" scheme in a pipelined processor. (5 marks) Explain the concept of a write-after-read hazard. How can they be resolved without affecting performance in an out-of-order processor? e