THIS IS TABLE 5-6 in the book, not sure what other information you need?

Consider changing instruction encoding of the processor given in Table 5-6 in the textbook from mixed of fixed vertical and horizontal formats to just fixed vertical format. Keep instruction format length 16 bits long by adjusting number of bits allocated to the address field. a) Give instruction format by identifying its fields, number of bits allocated to each field, list of instructions and their corresponding new op codes, list of addressing modes and their corresponding binary codes. b) Rewrite Fetch Cycle, and execute Cycle for instructions ADD, CLA, and INP by listing their micro-operations along with their corresponding control functions. Fetch R'To: ARPC R'T IR M[AR), PC + PC + 1 R'Tz: Do, ..., D, Decode IR(12-14). AR-IR(0-11), I-IR(15) DIT3: ARM[AR] Decode Indirect Interrupt: T.TT(IEN) (FGI + FGO): R=1 RT: AR0, TR PC RT: MAR-TR, PC+0 RT: PC PC + 1, IENO, RO, SCO Memory-reference: AND ADD LDA STA BUN BSA D.T.: DRM[AR] D.Ts: AC AC ADR, SC+0 D.T.: DR MAR] DITS: AC + AC + DR, E-Cout; SCO D2T.: DR+MAR D2Ts: AC DR, SCO D.T.: M[AR] AC, SCO D.T. PC+AR, SC-0 DT: MAR] PC, ARFAR + 1 Dsts: PC+AR, SC+0 D.T.: DR MAR] D.TS: DR DR + 1 D.T.: M[AR]-DR, if(DR = 0) then (PC +PC + 1), SCO ISZ Register-reference: CLA CLE CMA CIR DI'T, = r (common to all register-reference instructions) IR() = B (i = 0, 1, 2, ..., 11) r: SCO rB11: AC=0 rB10: E=0 By: AC AC rB, EE B.: AC +shr AC, AC(15) E, E AC(O) B.: AC +shl AC, AC(0) E, EAC(15) By: AC AC + 1 B.: If (AC(15) = 0) then (PC PC + 1) rBy: If (AC(15) = 1) then (PC PC + 1) B2: If (AC = 0) then PC PC + 1) B: If (E = 0) then (PC +PC + 1) rB: SO CIL INC SPA SNA SZA SZE HLT Input-output: INP OUT SKI SKO ION IOF D-IT, = p (common to all input-output instructions) IRO) = B. (i = 6, 7, 8, 9, 10, 11) p: SCO pB: AC(0-7) INPR, FGI 0 pB 10 OUTRAC(0-7), FGO=0 PB: If (FGI = 1) then (PC PC + 1) pBy: If (FGO = 1) then (PC+PC + 1) pB: IEN-1 pB: IENO