This problem about multicycle cpu datapath, and calculating delay.

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5. Multi-Cycle Implementation. For this problem, please refer to the multi-cycle datapath drawn below. The processor obeys the following conditions. 1) The ALU can perform either ADD i.e. A B) or SUB (i.e. A B) and the output NEG indicates if the result is negative. 2) The NEG signal, after being delayed one cycle, is fed through the controller. 3) The control state machine is reset to 0 every time the P register (program counter) is written, otherwise, the state machine advances by one every cycle. 4) Each instruction for this multi-cycle datapath contains two immediates, termedxi and X2 each of which is independently sign-extended. 5) The clock only applies to the write operation of DMEM, and has no effect on the read operation. MX1 PE EN MEM SIGN EXT ALU X1 ADR AE SIGN EXT EN Neg DMEM RE ADR EN DIN TE EN MX2 5. Multi-Cycle Implementation. For this problem, please refer to the multi-cycle datapath drawn below. The processor obeys the following conditions. 1) The ALU can perform either ADD i.e. A B) or SUB (i.e. A B) and the output NEG indicates if the result is negative. 2) The NEG signal, after being delayed one cycle, is fed through the controller. 3) The control state machine is reset to 0 every time the P register (program counter) is written, otherwise, the state machine advances by one every cycle. 4) Each instruction for this multi-cycle datapath contains two immediates, termedxi and X2 each of which is independently sign-extended. 5) The clock only applies to the write operation of DMEM, and has no effect on the read operation. MX1 PE EN MEM SIGN EXT ALU X1 ADR AE SIGN EXT EN Neg DMEM RE ADR EN DIN TE EN MX2