This problem considers whether or not it is (theoretically) possible for a set-associative cache to perform worse-i.e. have a higher miss rate-than a direct mapped cache of the same total size. Consider a four-line direct mapped cache and two-way set associative cache with two sets (for a total of four cache lines). If possible, show a memory access pattern -i.e. a series of memory addresses-that will produce more misses in the set-associative cache that in the direct-mapped cache. If it is not possible to create such an access pattern, give a simple rationale explaining why it is not possible 2. This problem considers whether or not it is (theoretically) possible for a set-associative cache to perform worse-i.e. have a higher miss rate-than a direct mapped cache of the same total size. Consider a four-line direct mapped cache and two-way set associative cache with two sets (for a total of four cache lines). If possible, show a memory access pattern -i.e. a series of memory addresses-that will produce more misses in the set-associative cache that in the direct-mapped cache. If it is not possible to create such an access pattern, give a simple rationale explaining why it is not possible 2