This question asks you to add sra and srai support to the RISC$-$V datapath. These instructions takes the following format:

b$)$ Show the modified $($if any$)$ control signals for all of the ALU operations.

c$)$ Complete the control signals table below for the execution of the two new instructions in the single$-$cycle datapath after your modifications.

$\backslash$table$[[$CONTROL LOGIC SIGNALS$],[$INPUTS$,$OUTPUTS$],[$Instr$,\backslash$table$[[$Opcode$],[($instr$\_6.\mathrm{.}0)]],\backslash$table$[[$Funct$3],[($instr $14.\mathrm{.}12)]],\backslash$table$[[$Funct$7],[($Instr$\_30)]],$ImmSrc,RegWrite,AluSrc,AluOp,MemWrite,ResultSrc,Branch$],[$sra$,,,,,,,,,,],[$srai$,,,,,,,,,,]]$sra rd$,$ rs$1,$ rs$2$

srai rd$,$ rs$1,$ uimm

See the details of these instructions in the RISC$-$V Reference card.

a$)$ Modify the ALU design in the datapath shown below to add functionality for sra and srai. You only need to show the additions$/$modifications to the ALU design discussed in class and available in the notes on Canvas. You do not need to show the entire datapath in your answer. Clearly label your inputs and outputs.

b$)$ Show the modified $($if any$)$ control signals for all of the ALU operations.

c$)$ Complete the control signals table below for the execution of the two new instructions in the single$-$cycle datapath after your modifications.