This question has three parts a , b and c . They cant be seperated in different questions as they are all related . They must be answered all together. The tutor can arrange with chegg to deduct more quetions from my account as i said this question can not be answered.

For a direct mapped cache design with a 32-bit address, the following bits of the address used to access the cache: Tag index Offset 3-0 11-12 Starting from power on the following byte-addressed cache references are recorded in sequence of from left to right: Address (decimal) 1000 3100 2018 125 130 10 a) What is the cache block site in words) How many entre does the cache love? (Show your work for full credit) b) How many blocks are replaced? What is the hit ratio? Show your work Lit the final state of the cache in the title below, with each vatentry represented as record of index tag.data Index (decimal) Tag (decimal Data (MEM adidini