Traffic lights controller Project, You are required to implement two (2) traffic signals at a crossroads, with only one-directional traffic, whose time duration of green light should be proportional to the difference in the number of cars stopped at both signals. The color of the traffic signals is only red and green. Write a Verilog code with structural modeling for this project with detail comments that is to be implemented on FPGA. Draw a detailed block diagram and state diagram of the design. The operations that should be performed are as below: There are two seven-segments in your design to show the number of cars stopped at the respective signals. Thus, the maximum cars that can be at a signal is 9. The number of cars at a particular signal can be changed by two buttons, the AddCar and the NextSignal buttons. The Next Signal button selects one of both signals in an alternating fashion. The Add Car button adds one car to the selected signal on each button press. Cars can be added at any time it does not matter if the signal is green or red. When there are zero cars on each signal, the default time for the green light of each is 5 seconds. The time for which each signal will stay green should be proportional to the difference in the number of cars at each signal. If the difference is greater than 3 then the time for green light of the signal with the greater number of cars should increase by the number of seconds equal to the difference minus 3.When a signal is green, its car number should start to reduce by one car every second. The reducing number should be shown on the seven-segment display representing the count of cars for that signal.