true and false

true and false

(a) The pipelining technique achieves concurrency by replicating the hardware module. (b) Increasing the degree of associativity of a set-associative cache will increase the miss rate. (c) The hit rate can be increased by splitting a unified cache into two caches of equal size, one for instructions and one for data. (d) RISC architecture has a microarchitecture layer. (e) MIMD architecture consists of a single control unit and multiple processing elements. (f) Fully associative caches have faster access than direct-mapped caches. (g) To address a 256-cell memory the address has to have at least 8 bits. (h) In a 2-way set associative cache, there are two cache blocks in a set. (i) 01000010