True OR False ?

1- a 2-way superscalar processor has a peak IPC of 0.5?

2- superscalar processors are processors having deeper pipeline (i.e. pipeline with more stages)?

3- Dynamic (Out-of-order) superscaler processors do not guarantee that instructions are written back in strict program order ?

4- A two-bit predictor performs better than a single bit predictor even if the conditional branch is executed exactly once?

5- The two-bit predictor is an example of a dynamic branch predictor?

6- When compared to a single cycle processor. a pipelined processor always result in lower average CPI executing the same program?

7- A processor function correctly regardless of its branch miss-prediction rate?

8- There can never be any control hazard in a single-cycle processor?

9- A branch history table provides the predicted target address for fetching instruction ?

10 - Branch miss-prediction increases CPI of the running program?