Trying to get a VHDL 4 bit adder test bench to work. Any suggestions on what I'm doing wrong? My test bench isn't populating the correct results.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY fourbitadder_vhd_tst IS

END fourbitadder_vhd_tst;

ARCHITECTURE fourbitadder_arch OF fourbitadder_vhd_tst IS

-- constants

-- signals

SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL B : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL carry : STD_LOGIC;

SIGNAL cin : STD_LOGIC;

SIGNAL Sum : STD_LOGIC_VECTOR(3 DOWNTO 0);

COMPONENT fourbitadder

PORT (

A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

carry : OUT STD_LOGIC;

cin : IN STD_LOGIC;

Sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)

);

END COMPONENT;

BEGIN

i1 : fourbitadder

PORT MAP (

-- list connections between master ports and signals

A => A,

B => B,

carry => carry,

cin => cin,

Sum => Sum

);

init : PROCESS

-- variable declarations

BEGIN

-- code that executes only once

WAIT;

END PROCESS init;

always : PROCESS

-- optional sensitivity list

-- ( )

-- variable declarations

BEGIN

wait for 100 ns;

A <= "0000";

B <= "0000";

cin <= '0';

wait for 100 ns;

A <= "0000";

B <= "0001";

cin <= '1';

wait for 100 ns;

A <= "0001";

B <= "0001";

cin <= '0';

wait for 100 ns;

A <= "0010";

B <= "0001";

cin <= '0';

wait for 100 ns;

A <= "0010";

B <= "0011";

cin <= '0';

WAIT;

END PROCESS always;

END fourbitadder_arch;

I mainly need help with the last "BEGIN" section.