Two memories M$1,$M$2$ having: enables CS$1,$CS$2$; full warning flags f$1,$f$2$; empty warning flags e$1,$e$2$ respectively. A full warning flag is a

signal to indicate when the memory is full. An empty warning flag is a signal to indicate when the memory is empty. when both the

memories are connected to CPU through a common address bus and common data bus. what is the best digital logic for CS$1,$ CS$2$ if M$1$ is

preferred when both the memories are not full $?$ and M$2$ is preferred only after M$1$ is full. note : $"+","\text{'}","."$ are logical OR$,$ negation,

logical AND respectively

A$.CS2=e{1}^{\text{'}}*e2$;$CS1=e1$

B$.CS2=e1.e{2}^{\text{'}}$;$CS1=e^{\text{'}}$

C$.$ CS$2=$ f$1\text{'}.$f$2$;CS$1=$ f$1$

D$.CS2=f1.f{2}^{\text{'}}$;$CS1=f{1}^{\text{'}}$