Question: TYPE array 1 IS ARRAY ( 7 DOWNTO 0 ) OF STD _ LOGIC; TYPE array 2 IS ARRAY ( 3 DOWNTO 0 , 7

TYPE array1 IS ARRAY (7 DOWNTO 0) OF STD_LOGIC;
TYPE array2 IS ARRAY (3 DOWNTO 0,7 DOWNTO 0) OF STD_LOGIC;
TYPE array3 IS ARRAY (3 DOWNTO 0) OF array1;
SIGNAL a : BIT;
SIGNAL b : STD_LOGIC;:
SIGNAL x : array1;
SIGNAL y : array2;
SIGNAL w : array3;
SIGNAL z : STD_LOGIC_VECTOR (7 DOWNTO 0);
Determine the dimensions (1Dx1D,2D,1D, or scalar) of the VHDL signal given and if the operations are legal or illegal:
a <= x(2);
b <= x(2);
b <= y(3,5);
b <= w(5)(3);
y(1)(0)<= z(7);
x(0)<= y(0,0);
x <="1110000";
a <="0000000";
y(1)<= x;
w(0)<= y;
w(1)<=(7=>'1', OTHERS=>'0');
y(1)<=(0=>'0', OTHERS=>'1');
w(2)(7 DOWNTO 0)<= x;
w(0)(7 DOWNTO 6)<= z(5 DOWNTO 4);
x(3)<= x(5 DOWNTO 5);
b <= x(5 DOWNTO 5);
y <=((OTHERS=>'0'),(OTHERS=>'0'),(OTHERS=>'0'),"10000001");
z(6)<= x(5);
z(6 DOWNTO 4)<= x(5 DOWNTO 3);
z(6 DOWNTO 4)<= y(5 DOWNTO 3);
y(6 DOWNTO 4)<= z(3 TO 5);
y(0,7 DOWNTO 0)<= z;
w(2,2)<='1';

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