uppose we had a CPU design that can only do addq instructions as presented in the lecture, and we want to augment it to also support a new increment instruction: ncq REGISTER Question 1 (4 points) (see above) Which machine code encoding for this instruction would be possible to implement and require the fewest changes to the logic between the instruction memory and the register file A. 1 byte total; first byte: 0xx (most sig 4 bits), register number (least sig 4 bits); B. 1 byte total; first byte: register number (most significat 4 bits), 0xF (least sig 4 bits) C. 2 bytes total; first byte: 0xE0; second byte: 0xF (most sig 4 bits), register number (least sig 4 bits) D. 2 bytes total; first byte: 060; second byte: 01 (most sig 4 bits), register number (least sig 4 bits) E. none of the above; none of these are possible to implement Comments: Question 2 ( 3 points) (see above) To implement this instruction memory, we would likely add a new MUX to control Select all that apply. A. the address input to the instruction memory (pc in HCLRS) B. the register value input to the register file (reg_inputB or reg_inputM in HCLRS) C. one of the inputs into the ALU