Urgent!!!!!. Can someone please help with 3.5. 3.5 please, now other. I got all the rest of it

3.4 Use the scenario from Problem 3.1 a LO, except there is a nonzero processing delay for both virtual circuit switching (Tvc) and datagram switching (TD). Processing delay is always defined as the time per node to process a packet. This processing delay is only incurred for the nodes which send packets, which includes processing time at the first node. The processing delay for datagram switching is always larger, since the node has to make routing decisions instead of just switching decisions for getting the packet to its destination. Assume the processing delay for a virtual circuit switched packet at each node is TVC F 0.0035 s. Now compare with datagram packet switching. Find the range of processing delays (TD). for which virtual circuit switching has a lower end-to-end delay than datagram packet switching 3.5 Given now is the scenario from Problem 3.4 0, but TD 14.5 ms and Tyc 3 ms. Assume the number of packets to transfer is unknown. For what range numbers of packets would the end-to-end delay to transfer all of the packets be less for virtual circuit switching than the datagram approach? For what range of sizes of the total message length does this correspond