urgent !!!!!

the number is 5

The Single-cycle computer in Figure 8.23 executes the instruction is stored (OOCB) hex address in the instruction memory described below. BNZ R2, -(Number) (Branch Not Zero R2, - Number) (Number is last number of your school number) (8p) Complete the following table, giving the binary instruction decoder outputs from Figure 8.23 during execution of the instruction: DA AA BA MB FS MD RW MW PL JB AA BA ME (10p) Complete the following table, giving the instruction in binary for the single-cycle computer that executes the instruction (if any field is not used, give it the value 0); Opcode DR SA SB or Operand DR | SA (7p) If -5 is loaded in the R2 register initially, calculate the hex value of the new content of the PC value after executing this command. PC Address Instruction memory Instruction Diagram of a (Hardwired) Programmable Computer RW D Register DA file AA BA Zero till Constant in Instruction decoder 1 0 MUX B MB Bus A Bus B Address out Data out MW Data Memory DB AMF MRM A A ABS DW W CONTROL FS B Data in Address V+ Function unit Data memory C. N+ Z+ Data out Data in MD 0 1 MUX D Bus D DATAPATH The Single-cycle computer in Figure 8.23 executes the instruction is stored (OOCB) hex address in the instruction memory described below. BNZ R2, -(Number) (Branch Not Zero R2, - Number) (Number is last number of your school number) (8p) Complete the following table, giving the binary instruction decoder outputs from Figure 8.23 during execution of the instruction: DA AA BA MB FS MD RW MW PL JB AA BA ME (10p) Complete the following table, giving the instruction in binary for the single-cycle computer that executes the instruction (if any field is not used, give it the value 0); Opcode DR SA SB or Operand DR | SA (7p) If -5 is loaded in the R2 register initially, calculate the hex value of the new content of the PC value after executing this command. PC Address Instruction memory Instruction Diagram of a (Hardwired) Programmable Computer RW D Register DA file AA BA Zero till Constant in Instruction decoder 1 0 MUX B MB Bus A Bus B Address out Data out MW Data Memory DB AMF MRM A A ABS DW W CONTROL FS B Data in Address V+ Function unit Data memory C. N+ Z+ Data out Data in MD 0 1 MUX D Bus D DATAPATH