USE BEHAVIORAL MODELLING. Construct VDL code for the given RTL diagram.

Present a piece of VDL source code according to presented RTL diagram. Memory cell (register), next state logic and output logic should be separated in presented piece of code. (2 points) entity sum is port btn: in std_logic; output: out syd_logic_vector (3 downto 0)); end sum; sum_reg 4 output type casting +1 sum_next 4 d 9 clk btn Present a piece of VDL source code according to presented RTL diagram. Memory cell (register), next state logic and output logic should be separated in presented piece of code. (2 points) entity sum is port btn: in std_logic; output: out syd_logic_vector (3 downto 0)); end sum; sum_reg 4 output type casting +1 sum_next 4 d 9 clk btn