Use the Direct-Mapped Cache Simulator: https://www3.ntu.edu.sg/home/smitha/ParaCache/Paracache/dmc.html Assume we have a 64Kbyte of RAM and direct-mapped byte-addressed cache
Question:
Use the Direct-Mapped Cache Simulator:
https://www3.ntu.edu.sg/home/smitha/ParaCache/Paracache/dmc.html
- Assume we have a 64Kbyte of RAM and direct-mapped byte-addressed cache with capacity 256 Bytes and block size of 32 Bytes. Use Write Policies Write Back & Write On Allocate.
Answer the following questions:
How many Memory Blocks in RAM?
How many Memory Blocks in the Cache?
How many bits is the Cache TAG?
How many bits is the Cache Index?
How many bits is the Cache Offset?
Manually enter the provided instructions into the simulator to fill in the following tables:
L/S | Address (Hex) | Tag (Binary) | Index (Binary) | Offset (Binary) | RAM Block (Hex) |
Store | 0x8132 | ||||
Store | 0xcf15 | ||||
Store | 0xbb3b | ||||
Load | 0x9a6c | ||||
Load | 0x6f35 | ||||
Store | 0xc85f | ||||
Store | 0xd12e | ||||
Load | 0x55a4 | ||||
Load | 0x111f | ||||
Load | 0x1716 | ||||
Store | 0x51a1 | ||||
Load | 0x960c | ||||
Load | 0xa1bb | ||||
Store | 0xbaba | ||||
Load | 0xa0b7 | ||||
Load | 0xbae5 |
Final State of the Direct-Mapped Cache Table (screenshot)
2.. Assume we have a 64Kbyte of RAM and 4-way set associative byte-addressed cache with capacity 256 Bytes and block size of 32 Bytes. Use a Replacement Policy of LRU & Write Policies of Write Back & Write on Allocate.
Answer the following questions:
How many Memory Blocks in RAM?
How many Memory Blocks in the Cache?
How many bits is the Cache TAG?
How many bits is the Cache Index?
How many bits is the Cache Offset?
Manually enter the provided instructions into the simulator to fill in the following tables:
L/S | Address (Hex) | Tag (Binary) | Index (Binary) | Offset (Binary) | RAM Block (Hex) |
Store | 0x8132 | ||||
Store | 0xcf15 | ||||
Store | 0xbb3b | ||||
Load | 0x9a6c | ||||
Load | 0x6f35 | ||||
Store | 0xc85f | ||||
Store | 0xd12e | ||||
Load | 0x55a4 | ||||
Load | 0x111f | ||||
Load | 0x1716 | ||||
Store | 0x51a1 | ||||
Load | 0x960c | ||||
Load | 0xa1bb | ||||
Store | 0xbaba | ||||
Load | 0xa0b7 | ||||
Load | 0xbae5 |
Final State of the Direct-Mapped Cache Table (screenshot)