Question: use verilog to write a code for : Design a synchronous FIFO with 32 entries and data width of 15 bits Implement single bit even

use verilog to write a code for :

Design a synchronous FIFO with 32 entries and data width of 15 bits

Implement single bit even parity check

Parity bit will be MSB in the memory

Read and write will generate and check parity

Full and empty pointer.

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