Use VHDL to create a computational unit that can compute the following operations on $4$

bit operands:

AND, OR$,$ NAND, NOR

with a data width parameter set to $4,$ an architecture that has $3$ rows and $4$ columns with

the second row being a set of $)$ that have connectivity with their inputs being

connected to the first row of $CU$ outputs.

They will deliver the first rows output to the CU input of the selected path for one of the

$CU$ inputs in the third row. A drawing can be found below.