Using $90$ nm process technology node with SOI CMOS wafers, your goal is to achieve less than $1$ nW standby dissipation at room temperature. The subthreshold parameter for SOI CMOS is given as m $=1\mathrm{.}06.$ Assuming a supply voltage of $0\mathrm{.}4$V$,$ VTN $=|$VTP$|=0\mathrm{.}1$V$,$ and gate oxide thickness of $3$ nm for the symmetric low$-$power CMOS inverter, calculate the respective gate widths of NMOS and PMOS devices.