Using AMD VIVADO tool, write VHDL code for a CRC$-8$ hardware for $8-$

bit data input and CRC polynomial input. Use VHDL behavioral modeling to

design the CRC$-8$ hardware with asynchronous active low reset. Do not use the

look$-$up table method.

Simulate and test the CRC$-8$ design using a VHDL test bench for at least two test

cases with different CRC polynomials. Capture the waveforms and verify the

results.

data input is $8$ bits, polynomial input is $9$ bits. use logical left shifts and XOR division

Please test using two different test cases of polynomial$($G$)$ and data$($D$).$ Include waveforms as well