2. Using Xilinx's Vivado Design Tool design a 1 multiplexer in Verilog ting Behavioral form. Simulate this code and compare the simulation output to the truth table developed for the experiment. Use the count up option in the UUT waveform tool to vary the select inputs from 000 binury do 111 hinary 3. Click on Run Synthesis on saving the project. Once it is successfully completed. Click on Run Implementation 4 4 Once RTL analysis is performed, another standard layout called the 10 Planning is available. Click on the drop-down button and select the 10 Planning layout. Expand the Open Elaborated Design entry under the RTL Analysis tasks of the Flow Navigator pane and click on Schematic to obtain the design that is created. Obtain a screenshot of the generated diagram to reproduce it in the report $ Expand the Open Synthesized Design under Synthesis tab of the Flow Navigator to obtain the Package View of the design generated. Assign the package pins accordingly. Connect the input word to SW-SWIS, the selecter lines to SWA-SW6, and the output should be linked to LED on the BASYS3 band. The value of Lo Std for all of these switches should be set to LVCMOS33" 46 | Once the package pins are assigned, save the constraints file by clicking "File">Suve Constraints. Name and save the constraint file 7. Then we should simulate the design using the XSim Simulator. Click Add Sources under the Project Manager tasks of the Flow Navigator pane Select the Add or Create Simulation Sources option and click Next. We create a new file for simulation ** Sim.". For the simulation file, we don't need to set the Lo Click OK in this step & Double click on the Sim." in the Sources window to type define the testbench as done in previous labs making sure to generate all combinations of the inputs (8 bits for the input word and 3 bits for the select lines) 9. Click on Run Simulation > Run Behavioral Simulation under the Project Manager tasks of the Flow Navigator window. The test bench and serce files are compiled and the XSim simulator is run assuming no errors). Click on the Zoom Fit" icon to see all the spectrum of simulation 10. In the last part, let's click on the Generate Bitstream on the left hand menu towards the bottom. Vivado runs through both Run Synthesis and Run Implementation before it generates the bitstream automatically. This proces generates the BIT file needed to program the FPGA 11. Go to "Flow > Hardware Manager in the toolbar Tum on your bound by pushing up its power switch. Click on "Auto Connection in the Hardware Manager window Click on the board name "c7a35t (1)". In the opened "Hardware Device Properties window, make sure the bit file is selected for the Programming file". Next, right click on the board name and choose "Program Derice.... Once the status of the board goes to "Programmed", then you can check the design functionality on the board by changing the state of switches 2. Using Xilinx's Vivado Design Tool design a 1 multiplexer in Verilog ting Behavioral form. Simulate this code and compare the simulation output to the truth table developed for the experiment. Use the count up option in the UUT waveform tool to vary the select inputs from 000 binury do 111 hinary 3. Click on Run Synthesis on saving the project. Once it is successfully completed. Click on Run Implementation 4 4 Once RTL analysis is performed, another standard layout called the 10 Planning is available. Click on the drop-down button and select the 10 Planning layout. Expand the Open Elaborated Design entry under the RTL Analysis tasks of the Flow Navigator pane and click on Schematic to obtain the design that is created. Obtain a screenshot of the generated diagram to reproduce it in the report $ Expand the Open Synthesized Design under Synthesis tab of the Flow Navigator to obtain the Package View of the design generated. Assign the package pins accordingly. Connect the input word to SW-SWIS, the selecter lines to SWA-SW6, and the output should be linked to LED on the BASYS3 band. The value of Lo Std for all of these switches should be set to LVCMOS33" 46 | Once the package pins are assigned, save the constraints file by clicking "File">Suve Constraints. Name and save the constraint file 7. Then we should simulate the design using the XSim Simulator. Click Add Sources under the Project Manager tasks of the Flow Navigator pane Select the Add or Create Simulation Sources option and click Next. We create a new file for simulation ** Sim.". For the simulation file, we don't need to set the Lo Click OK in this step & Double click on the Sim." in the Sources window to type define the testbench as done in previous labs making sure to generate all combinations of the inputs (8 bits for the input word and 3 bits for the select lines) 9. Click on Run Simulation > Run Behavioral Simulation under the Project Manager tasks of the Flow Navigator window. The test bench and serce files are compiled and the XSim simulator is run assuming no errors). Click on the Zoom Fit" icon to see all the spectrum of simulation 10. In the last part, let's click on the Generate Bitstream on the left hand menu towards the bottom. Vivado runs through both Run Synthesis and Run Implementation before it generates the bitstream automatically. This proces generates the BIT file needed to program the FPGA 11. Go to "Flow > Hardware Manager in the toolbar Tum on your bound by pushing up its power switch. Click on "Auto Connection in the Hardware Manager window Click on the board name "c7a35t (1)". In the opened "Hardware Device Properties window, make sure the bit file is selected for the Programming file". Next, right click on the board name and choose "Program Derice.... Once the status of the board goes to "Programmed", then you can check the design functionality on the board by changing the state of switches