Question: Using DATAFLOW design ( concurrent ) Code and simulate a 7 4 XX 1 3 8 3 to 8 decoder ( Assume we are using

Using DATAFLOW design (concurrent) Code and simulate a 74XX1383 to 8 decoder
(Assume we are using the XILINX ARTIX 7 model xc7a35tcpg236-1 FPGA from XILINX)
Define and use a Test Bench for the device
Show and explain results

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