Using DC simulations, plot the Gate characteristics (Drain Current on Y-axis Vs Gate Voltage on X-axis) on a linear and log scale (Y-axis) of the following Transistors whose models are available in the ASAP 7nm PDK provided. Assume a Supply Voltage, VDD = 0.7V and a width of '3 fins' for each of the transistors (i) - (iii) and a width of 1 fin for SRAM NFET and a width of 1 fin for the SRAM PFET (a) From the Gate characteristics, extract the VT of each of the Transistors for the 2 cases of VDS = 10mV and 0.7V NFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM PFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM Show the Values of VT using a Bar diagram for NFETs and PFETs