Using full adders and any any other gates build a $6-$bit adder$/$subtractor with the following ports.

typedef logic signed $[5$:$0]$ i$6\_$t;

module add$\_$sub$\_6($output i$6\_$t result, input i$6\_$t a$,$ b$,$ input logic add$\_$sub $)$;

The i$6\_$t type is defined in the main test bench. It specifies a $6-$bit signed number. When add$\_$sub is $1,$ the add$\_$sub$\_6$ performs addition. It subtracts when add$\_$sub is $0.$ Notice that the final carry is discarded. The typedef for i$6\_$t is:

typedef logic signed $[5$:$0]$ i$6\_$t;

$//$ insert fa

module add$\_$sub$\_6($output i$6\_$t result,

input i$6\_$t a$,$ b$,$ input logic add$\_$sub $)$;

$//$ complete with fa and other gates

endmodule