Using JK flip$-$flops in LogiSim, design a $4-$bit register that can either load new $($parallel$)$ data or

store the existing data. The inputs to the register will be:

$4$ data bits $($for the parallel data load$)$

$1$ select bit $($referred to as LOAD$).$ If LOAD $=1$ new parallel data is loaded, otherwise the

existing values in the register are maintained.

$1$ enable bit $($referred to as EN$).$ This bit is used to turn on or enable your register. It

overrides the LOAD bit. If EN $=0$ the existing values in the register are maintained, regardless

of the state of the LOAD bit. If EN $=1$ the register either loads new data or maintains the

existing, as specified by the LOAD bit.

$[5]$ You are required to create a design for this register using four JK flip$-$flops and four $2-$to$-1$

multiplexers and any additional gates that you may need. Demo loading a new value and retaining

the exiting value of this register