Design a four-bit shift register (not a universal shift register) with parallel load using D flip- flops. (See Figs. 6.2 and 6.3.) There are two control inputs: shift and load. when shift = 1, the content of the register is shifted toward Aj by one position. New data are transferred into the register when load-1 and shift = 0, If both control inputs are equal to 0, the content of the register does not change. (HDL-see Problem 6.35(c), (d)) 6.6 Design a four-bit shift register (not a universal shift register) with parallel load using D flip- flops. (See Figs. 6.2 and 6.3.) There are two control inputs: shift and load. when shift = 1, the content of the register is shifted toward Aj by one position. New data are transferred into the register when load-1 and shift = 0, If both control inputs are equal to 0, the content of the register does not change. (HDL-see Problem 6.35(c), (d)) 6.6