Question: Using ModelSim 2. Write the Verilog code, complete the timing diagram, and draw the resulting circuit using the OSU 0.5um library for a positive edge

Using ModelSim

2. Write the Verilog code, complete the timing diagram, and draw the resulting circuit using the OSU 0.5um library for a positive edge triggered flip flop with active low asynchronous reset and active low synchronous set. Synthesize the circuit (using "Synopsys Design Compiler"), report the final area, and provide the synthesis report of the inferred memory device. 25pts clk set data in data out

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