Using the ALU description in chapter $4($along with the lecture slides$),$ design, code, and test a $4-$bit ALU that implements the functional table provided to you $($e$.$g$.$ if you are implementing A $+$ B$,$ it should be able to add a number like A$=1001$ and B$=0011).$ First, please create the ALU using the dataflow and structural models. At a minimum, create a module for:

Half Adder HA

Full Adder FA

Carry Extender CE

Logic Extender LE

Arithmetic Extender AE$.$

I personally also created one for the "Slice" of the ALU as this greatly

simplifies the final VHDL module connecting them. Time how long it takes you to create the ALU using the dataflow model.

After you have designed and tested the ALU using the dataflow model, recreate the ALU using the Behavior $($i$.$e$.$ using Process Statement$)$ model, and time how long that process takes.

Please use Xilinx Vivado in VHDL$.$ Thank you!