Question: Using the pipeline latencies below, unroll the following loop with two iterations so it may be scheduled with reduced delay. Use register renaming, instruction rearrangement,

Using the pipeline latencies below, unroll the following loop with two iterations so it may be scheduled with reduced delay. Use register renaming, instruction rearrangement, or delay slot filling to optimize the unrolled loop. Assume a one-cycle delayed branch.

Loop: LD F0, 0(R1) MULTD F0,F0,F2 LD F4, 0(R2) ADDD F0, F0, F4 SD 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R1, Loop

The latencies in clock cycles are: 3 for FP ALU Op producing a result for another FP ALU Op 2 for FP ALU Op producing a result for SD 1 for Load Double producing a result for a FP ALU Op 0 for Load Double producing a result for a Store Double

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