Question: Using UDP, design a 5-inputs majority circuit, the circuit has 5 inputs X1, X2, X3, X4, and X5 and one output Z1, the value of

 Using UDP, design a 5-inputs majority circuit, the circuit has 5

Using UDP, design a 5-inputs majority circuit, the circuit has 5 inputs X1, X2, X3, X4, and X5 and one output Z1, the value of the output is 1 when the majority of inputs are ls, that's it, otherwise output is 0. Create your Verilog code for this circuit then write Test Bench file file

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