Verilog ser Defined Primitives DP Exercise 4: Using UDP, design a 5-inputs majority circuit, the circuit has 5 inputs XI, X2, X3, X4, and X5 and one output ZI, the value of the output is 1 when the majority of inputs are 1s, that's it, otherwise output is 0. Create your Verilog code for this circuit then write Test Bench file. Verilog ser Defined Primitives DP Exercise 4: Using UDP, design a 5-inputs majority circuit, the circuit has 5 inputs XI, X2, X3, X4, and X5 and one output ZI, the value of the output is 1 when the majority of inputs are 1s, that's it, otherwise output is 0. Create your Verilog code for this circuit then write Test Bench file