Verilog Code:

module TtrfLght2(

output reg [7:0] LED, // LED array , has to be register type.

input [1:0] SW, // 2 bit vector for the Left turns EW and NS

input clk // clock signal

);

reg [2:0] state, next_state;

// Define alias for state values

parameter S0=3'b000,

S1=3'b001,

S2=3'b010,

S3=3'b011,

S4=3'b100,

S5=3'b101,

S6=3'b110, // Not used but defined as an example

S7=3'b111; // not used but defined as an example

// Change to next stat only on transition of clock,

always @(posedge clk)

state

// Define next state

always @(state or SW[0]) // State changes

case(state)

S0: case (SW) // For state validate al cases of SW 2 switches

2'b00: next_state=S1;

2'b01: next_state=S1;

2'b10: next_state=S1;

2'b11: next_state=S1;

endcase

S1: case (SW) // For state validate al cases of SW 2 switches

2'b00: next_state=S2;

2'b01: next_state=S4;

2'b10: next_state=S2;

2'b11: next_state=S4;

endcase

S2: case (SW) // For state validate al cases of SW 2 switches

2'b00: next_state=S3;

2'b01: next_state=S3;

2'b10: next_state=S3;

2'b11: next_state=S3;

endcase

S3: case (SW) // For state validate al cases of SW 2 switches

2'b00: next_state=S0;

2'b01: next_state=S0;

2'b10: next_state=S5;

2'b11: next_state=S5;

endcase

S4: case (SW) // For state validate al cases of SW 2 switches

2'b00: next_state=S2;

2'b01: next_state=S2;

2'b10: next_state=S2;

2'b11: next_state=S2;

endcase

S5: case (SW) // For state validate al cases of SW 2 switches

2'b00: next_state=S0;

2'b01: next_state=S0;

2'b10: next_state=S0;

2'b11: next_state=S0;

endcase

default next_state=S0;

endcase

always @(state) // Moore outputs

case(state)

S0: LED

S1: LED

S2: LED

S3: LED

S4: LED

S5: LED

//LED 7 indicates an undefined state output and the last 3 bits are the state value

default begin LED[2:0]

endcase

endmodule

Question:

[a]

[b]

[c]

[d]

[e]

[f]

All answer choices:

A. 26

B. 44

C. 25

D. 28

E. 30

F. 84

For the code provided below identify the sequence of outputs in hexadecimal to complete the sequence table below Present State SW Clock Period Next State in Hex 2b01 2b01 2 b01 2'b01 2b10 2b10 2'b10 2'b00 3 b011 (S3) 3'b000 (SO 3'b001 3'b000 (SO 3'b001 (S1) 8'H28 8H84 8H [a 8'H b 6 8H [d 3'b??? 3'b??? 8'H 0