VERILOG Sequence Generator Next with Boolean Expressions

Complete the VERILOG next_pattern module for the following sequence using Boolean expressions. The VERILOG next_pattern module should be designed by:

Drawing the state graph. Deriving the next state table. Using K-maps to simplify the function.

The next_pattern module provides the next state function for a Finite State Machine (FSM) that generates the following sequence of patterns:

12, 1, 14, 13, 5, 6, 7, 0, 10

The first pattern follows the last pattern.

Any patterns not in the sequence should be considered as do not cares. The next function will not be tested for these patterns.

module next_pattern(output logic [3:0] next, input logic [3:0] cur);

endmodule